1. Technical Field
The present invention relates to an apparatus and method of controlling an operation frequency in a DLL (Delay Locked Loop) circuit, and in particular, to an apparatus and method of controlling an operation frequency in a DLL circuit that reduces the time required for a delay locking operation.
2. Related Art
Generally, a DLL circuit is used to supply an internal clock having an earlier phase than a reference clock, which is obtained by converting an external clock, for a predetermined time. The internal clock is generated to allow a semiconductor memory apparatus having relatively high integration, such as a synchronous DRAM (SDRAM) or the like, to operate in synchronization with the external clock.
More specifically, if an external clock input through an input pin is input to a clock buffer, an internal clock is generated from the clock buffer. Subsequently, the internal clock controls a data output buffer to output data to the outside. At this time, the internal clock is delayed by the clock buffer from the external clock for a predetermined time, and output data from the data output buffer is delayed from the internal clock for a predetermined time and then output.
The output data is delayed from the external clock for a considerable amount of time and then output. Specifically, the time it takes data to be output after the external clock is applied, that is, an output data access time, becomes long.
In the related art, the phase of the internal clock is set to have a more advanced phase than the external clock for a predetermined time using the DLL circuit, such that output data can be output with no delay with respect to the external clock. That is, the DLL circuit receives the external clock and generates the internal clock having a more advanced phase than the external clock for a predetermined time. The internal clock is used as the reference clock in the data output buffer or the like.
As such, a predetermined amount of time is needed from when the DLL circuit performs the delay locking operation on the external clock until locking is completed. Generally, it is configured such that the DLL circuit completes the clock delay locking operation within 200 cycles of the loop. Accordingly, if the DLL circuit does not complete the clock delay locking operation within the 200 cycles due to PVT (Process, Voltage, and Temperature) and the like, an erroneous operation occurs. As a result, a semiconductor integrated circuit that uses the DLL circuit cannot accurately synchronize data with the clock. Further, in the semiconductor integrated circuit that includes the DLL circuit, during a test mode, tests in other areas cannot be performed until the DLL circuit completes the clock delay locking operation. Accordingly, the time required until the DLL circuit completes the delay locking operation has enormous influence on test efficiency of the semiconductor integrated circuit. In order to overcome the above-described problems, there is a need for a technology that reduces the time required for the clock delay locking of the DLL circuit. However, there is a technical limit to reducing the time required for the delay locking operation.